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december 2002 dsc-5304/05 1 ?2002 integrated device technology, inc. pin description summary description the idt71v65603/5803 are 3.3v high-speed 9,437,184-bit (9 megabit) synchronous srams. they are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus, they have been given the name zbt tm , or zero bus turnaround. features u u u u u 256k x 36, 512k x 18 memory configurations u u u u u supports high performance system speed - 150mhz (3.8ns clock-to-data access) u u u u u zbt tm feature - no dead cycles between write and read cycles u u u u u internally synchronized output buffer enable eliminates the need to control oe u u u u u single r/ w (read/write) control pin u u u u u positive clock-edge triggered address, data, and control signal registers for fully pipelined applications u u u u u 4-word burst capability (interleaved or linear) u u u u u individual byte write ( bw 1 - bw 4 ) control (may tie active) u u u u u three chip enables for simple depth expansion u u u u u 3.3v power supply (5%) u u u u u 3.3v i/o supply (v ddq ) u u u u u power down controlled by zz input u u u u u packaged in a jedec standard 100-pin plastic thin quad flatpack (tqfp), 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga). a 0 -a 18 address inputs input synchronous ce 1 , ce 2 , ce 2 chip enables input synchronous oe output enable input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write selects input synchronous clk clock input n/a adv/ ld advance burst address / load new address input synchronous lbo linear / interleaved burst order input static zz sleep mode input asynchronous i/o 0 -i/o 31 , i/o p1 -i/o p4 data input / output i/o synchronous v dd , v ddq core power, i/o power supply static v ss ground supply static 53 04 tb l 01 256k x 36, 512k x 18 3.3v synchronous zbt? srams zbt? feature 3.3v i/o, burst counter pipelined outputs idt71v65603 idt71v65803 address and control signals are applied to the sram during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. the idt71v65603/5803 contain data i/o, address and control signal registers. output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the idt71v65603/5803 to be suspended as long as necessary. all synchronous inputs are ignored when ( cen ) is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1, ce2, ce 2) that allow the user to deselect the device when desired. if any one of these three are not asserted when adv/ ld is low, no new memory operation can be initiated. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state two cycles after chip is deselected or a write is initiated. the idt71v65603/5803 have an on-chip burst counter. in the burst mode, the idt71v65603/5803 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the idt71v65603/5803 sram utilize idt's latest high-performance cmos process, and are packaged in a jedec standard 14mm x 20mm 100- pin thin plastic quad flatpack (tqfp) as well as a 119 ball grid array (bga) and 165 fine pitch ball grid array (fbga) . zbt and zero bus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron te chnology and motorola, inc.
6.42 2 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 -a 18 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk, adv/ ld low, cen low, and true chip enables. adv/ ld advance / load i n/a adv/ ld is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled hig h then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sampled high. r/ w read / write i n/a r/ w signal is a synchronous input that identifies whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place two clock cycles later. cen clock enable i low synchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs re main unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. each 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the idt71v65603/5803. ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. the zbt tm has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. ce 2 chip enable i high synchrono us active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip. ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock input to the idt71v65603/5803. except for oe , all timing references for the device are made with respect to the rising edge of clk. i/o 0 -i/o 31 i/o p1 -i/o p4 data input/output i/o n/a synchro nous data input/output (i/o) pins. both the data input path and data output path are registered and triggered by the rising edge of clk. lbo linear burst order i low burst order selection input. when lbo is high the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static input and it must not change during device operation. oe output enable i low asynchronous output enable. oe must be low to read data from the 71v65603/5803. when oe is high the i/o pins are in a high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. zz sleep mode i n/a asynchronous sleep mode input. zz high will gate the clk internally and power down the 71v65603/5803 to its lowest power consumption level. data retention is guaranteed in sleep mode. v dd power supply n/a n/a 3.3v core power supply. v ddq power supply n/a n/a 3.3v i/o supply. v ss ground n/a n/a ground. 5304tbl 02
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 3 functional block diagram clk dq dq dq address a [0:17] control logic address control di do input r egister 5304 drw 01a clock data i/o [0:31], i/o p[1:4] d q clk output register mux sel gate o e c e 1, ce2, c e 2 r/ w c e n adv/ l d b w x l b o 256kx36 bit memory array ,
6.42 4 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges recommended dc operating conditions notes: 1. v il (min.) = C1.0v for pulse width less than t cyc /2, once per cycle. functional block diagram symbol parameter min. typ. max. unit v dd core supply voltage 3.135 3.3 3.465 v v ddq i/o supply voltage 3.135 3.3 3.465 v v ss supply voltage 0 0 0 v v ih input high voltage - inputs 2.0 ____ v dd +0.3 v v ih input high voltage - i/o 2.0 ____ v ddq +0.3 v v il input low voltage -0.3 (1 ) ____ 0.8 v 5304 tbl 04 clk dq dq dq address a [0:18] control logic address control di do input r egister 5304 drw 01 clock data i/o [0:15], i/o p[1:2] d q clk output register mux sel gate o e c e 1, ce2, c e 2 r/ w c e n adv/ l d b w x l b o 512x18 bit memory array ,
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 5 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 b w 4 b w 3 b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (2) a 17 a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d n u (3) d n u (3) d n u (3) d n u (3) lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v ddq i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v ddq v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v ddq i/o 1 i/o 0 5304 drw 02 v dd (1) i/o 15 i/o p3 v dd (1) i/o p4 a 15 a 16 i/o p1 v dd (1) i/o p2 zz , recommended operating temperature and supply voltage pin configuration - 256k x 36 notes: 1. pins 14, 16 and 66 do not have to be connected directly to vdd as long as the input voltage is 3 vih. 2. pin 84 is reserved for a future 16m. 3. dnu=do not use. pins 38, 39, 42 and 43 are reserved for respective jtag pins: tms, tdi, tdo and tck. the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). top view 100 tqfp grade temperature (1) v ss v dd v ddq commercial 0 c to +70 c 0v 3.3v 5% 3.3v 5% industrial -40c to +85c 0v 3.3v 5% 3.3v 5% 5 304 tbl 05 notes: 1. t a is the "instant on" case temperature.
6.42 6 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges absolute maximum ratings (1) pin configuration - 512k x 18 119 bga capacitance (1) (t a = +25 c, f = 1.0mhz) top view 100 tqfp notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd terminals only. 3. v ddq terminals only. 4. input terminals only. 5. i/o terminals only. 6. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 7. t a is the "instant on" case temperature. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol rating commercial & industrial unit v te rm (2) terminal voltage with respect to gnd -0.5 to +4.6 v v te rm (3,6) terminal voltage with respect to gnd -0.5 to v dd v v te rm (4,6) terminal voltage with respect to gnd -0.5 to v dd +0.5 v v te rm (5,6) terminal voltage with respect to gnd -0.5 to v ddq +0.5 v t a (7) commercial operating temperature -0 to +70 o c industrial operating temperature -40 to +85 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 53 04 tbl 06 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 5304 tbl 07 10099989796959493929190 87868584838281 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 n c n c b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (2) a 18 a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 d n u (3) d n u (3) d n u (3) d n u (3) lb o a 15 a 14 a 13 a 12 a 11 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 nc nc v ddq v ss nc i/o p2 i/o 15 i/o 14 v ss v ddq i/o 13 i/o 12 v ss v dd i/o 11 i/o 10 v ddq v ss i/o 9 i/o 8 nc nc v ss v ddq nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc v ddq v ss nc i/o p1 i/o 7 i/o 6 v ss v ddq i/o 5 i/o 4 v ss v dd i/o 3 i/o 2 v ddq v ss i/o 1 i/o 0 nc nc v ss v ddq nc nc 5304 drw 02a v dd (1) nc nc v dd (1) nc a 16 a 17 nc v dd (1) a 10 zz , notes: 1. pins 14, 16 and 66 do not have to be connected directly to v dd as long as the input voltage is 3 v ih . 2. pin 84 is reserved for a future 16m. 3. dnu=do not use. pins 38, 39, 42 and 43 are reserved for respective jtag pins: tms, tdi, tdo and tck. the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 7 pf c i/o i/o capacitance v out = 3dv 7 pf 5304 tbl 07a 100 tqfp capacitance (1) (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv tbd pf c i/o i/o capacitance v out = 3dv tbd pf 5304 tb l 07b 165 fbga capacitance (1) (t a = +25 c, f = 1.0mhz)
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 7 notes: 1. j3, j5, and r5 do not have to be directly connected to v dd as long as the input voltage is 3 v ih . 2. a4 is reserved for future 16m. 3. dnu = do not use. pin u2, u3, u4, u5 and u6 are reserved for respective jtag pins: tms, tdi, tck, tdo and trst . the current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). pin configuration - 256k x 36, 119 bga top view pin configuration - 512k x 18, 119 bga top view 1234567 a v ddq a 6 a 4 a 8 a 16 v ddq b nc ce 2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 12 a 15 nc d i/o 16 i/o p3 v ss nc v ss i/o p2 i/o 15 e i/o 17 i/o 18 v ss v ss i/o 13 i/o 14 f v ddq i/o 19 v ss oe v ss i/o 12 v ddq g i/o 20 i/o 21 bw 3 bw 2 i/o 11 i/o 10 h i/o 22 i/o 23 v ss r/ w v ss i/o 9 i/o 8 j v ddq v dd v dd v dd v ddq k i/o 24 i/o 26 v ss clk v ss i/o 6 i/o 7 l i/o 25 i/o 27 bw 4 nc bw 1 i/o 4 i/o 5 m v ddq i/o 28 v ss cen v ss i/o 3 v ddq n i/o 29 i/o 30 v ss a 1 v ss i/o 2 i/o 1 p i/o 31 i/o p4 v ss a 0 v ss i/o 0 i/o p1 r nc a 5 lbo v dd a 13 t nc nc a 10 a 11 a 14 nc zz u v ddq dnu (3) dnu (3) dnu (3) v ddq 5304 drw 13a v dd(1) nc nc (2) ce 1 a17 v dd(1) v dd(1) , dnu (3) dnu (3) nc 1234567 a v ddq a 6 a 4 nc(2) a 8 a 16 v ddq b nc ce2 a 3 adv/ ld a 9 ce 2 nc c a 7 a 2 v dd a 13 a 17 nc d i/o 8 nc v ss nc v ss i/o 7 nc e nc i/o 9 v ss v ss nc i/o 6 f v ddq nc v ss oe v ss i/o 5 v ddq g nc i/o 10 bw 2 nc i/o 4 h i/o 11 nc v ss r/ w v ss i/o 3 nc j v ddq v dd v dd v dd v ddq k nc i/o 12 v ss clk v ss nc i/o 2 l i/o 13 nc nc bw 1 i/o 1 nc m v ddq i/o 14 v ss cen v ss nc v ddq n i/o 15 nc v ss a 1 v ss i/o 0 nc p nc i/o p2 v ss a 0 v ss nc i/o p1 r nc a 5 lbo v dd a 12 t nc a 10 a 15 nc a 14 a 11 zz u v ddq dnu (3) dnu (3) dnu (3) dnu (3) nc v ddq 5304 drw 13b nc dd(1) v dnu (3) v ss v ss ce 1 a18 v dd(1) v dd(1)
6.42 8 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. h1, h2, and n7 do not have to be directly connected to v dd as long as the input voltage is 3 v ih . 2. b9, b11, a1, r2 and p2 is reserved for future 18m, 36m, 72m, 144m and 288m, respectively. 3. dnu=do not use. pins p5, r5, p7 and r7 are reserved for respective jtag pins: tdi, tms, tdo and tck on future revisions. th e current die revision allows these pins to be left unconnected, tied low (v ss ), or tied high (v dd ). pin configuration - 256k x 36, 165 fbga pin configuration - 512k x 18, 165 fbga 1234567891011 anc (2) a 7 ce 1 bw 3 bw 2 ce 2 cen adv /ld a 17 a 8 nc bnc a 6 ce 2 bw 4 bw 1 clk r/ w oe nc (2) a 9 nc (2) ci/o p3 nc v ddq v ss v ss v ss v ss v ss v ddq nc i/o p2 di/o 17 i/o 16 v ddq v dd v ss v ss v ss v dd v ddq i/o 15 i/o 14 ei/o 19 i/o 18 v ddq v dd v ss v ss v ss v dd v ddq i/o 13 i/o 12 fi/o 21 i/o 20 v ddq v dd v ss v ss v ss v dd v ddq i/o 11 i/o 10 gi/o 23 i/o 22 v ddq v dd v ss v ss v ss v dd v ddq i/o 9 i/o 8 hv dd (1) v dd (1) nc v dd v ss v ss v ss v dd nc nc zz ji/o 25 i/o 24 v ddq v dd v ss v ss v ss v dd v ddq i/o 7 i/o 6 ki/o 27 i/o 26 v ddq v dd v ss v ss v ss v dd v ddq i/o 5 i/o 4 li/o 29 i/o 28 v ddq v dd v ss v ss v ss v dd v ddq i/o 3 i/o 2 mi/o 31 i/o 30 v ddq v dd v ss v ss v ss v dd v ddq i/o 1 i/o 0 ni/o p4 nc v ddq v ss dnu (3) nc v dd (1) v ss v ddq nc i/o p1 pncnc (2) a 5 a 2 dnu (3) a 1 dnu (3) a 10 a 13 a 14 nc r lbo nc (2) a 4 a 3 dnu (3) a 0 dnu (3) a 11 a 12 a 15 a 16 5304 tbl 25a 1234567891011 anc (2) a 7 ce 1 bw 2 nc ce 2 cen adv /ld a 18 a 8 a 10 bnc a 6 ce 2 nc bw 1 clk r/ w oe nc (2) a 9 nc (2) cnc ncv ddq v ss v ss v ss v ss v ss v ddq nc i/o p1 dnc i/o 8 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 7 enc i/o 9 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 6 fnc i/o 10 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 5 gnc i/o 11 v ddq v dd v ss v ss v ss v dd v ddq nc i/o 4 hv dd (1) v dd (1) nc v dd v ss v ss v ss v dd nc nc zz ji/o 12 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 3 nc ki/o 13 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 2 nc li/o 14 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 1 nc mi/o 15 nc v ddq v dd v ss v ss v ss v dd v ddq i/o 0 nc ni/o p2 nc v ddq v ss dnu (3) nc v dd (1) v ss v ddq nc nc pnc nc (2) a 5 a 2 dnu (3) a 1 dnu (3) a 11 a 14 a 15 nc r lbo nc (2) a 4 a 3 dnu (3) a 0 dnu (3) a 12 a 13 a 16 a 17 5304 tbl25b
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 9 synchronous truth table (1) partial truth table for writes (1) notes: 1. l = v il , h = v ih , x = dont care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state two cycles after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/ os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l, ce 2 = h on these chip enables. chip is deselected if any one of the chip enables is false. 6. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. 7. q - data read from the device, d - data written to the device. notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. 3. n/a for x18 configuration. cen r/ w chip (5) enable adv/ ld bw x address used previous cycle current cycle i/o (2 cycles later) l l select l valid external x load write d (7) l h select l x external x load read q (7) l x x h valid internal load write / burst write burst write (advance burst counter) (2) d (7) l x x h x internal load read / burst read burst read (advance burst counter) (2) q (7) l x deselect l x x x deselect or stop (3) hiz l x x h x x deselect / noop noop hiz h x x x x x x suspend (4) previous value 53 04 tb l 08 operation r/ w bw 1 bw 2 bw 3 (3) bw 4 (3) read hxxxx write all bytes l l l l l write byte 1 (i/o[0:7], i/o p1 ) (2) llhhh write byte 2 (i/o[8:15], i/o p2 ) (2) lhlhh write byte 3 (i/o[16:23], i/o p3 ) (2,3) lhhlh write byte 4 (i/o[24:31], i/o p4 ) (2,3) lhhhl no write l hhhh 53 04 tbl 09
6.42 10 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges linear burst sequence table ( lbo =v ss ) interleaved burst sequence table ( lbo =v dd ) functional timing diagram (1) notes: 1. this assumes cen , ce 1 , ce 2 , ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. da ta_out is valid after a clock-to-data delay from the rising edge of clock. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11100100 53 04 tb l 10 sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11000110 530 4 tb l 11 n+29 a29 c29 d/q27 address (2) (a0 - a17) control (2) (r/ w ,adv/ ld , bw x) data (2) i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q28 n+31 a31 c31 d/q29 n+32 a32 c32 d/q30 n+33 a33 c33 d/q31 n+34 a34 c34 d/q32 n+35 a35 c35 d/q33 n+36 a36 c36 d/q34 n+37 a37 c37 d/q35 5304 drw 03 ,
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 11 notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. read operation (1) device operation - showing mixed load, burst, deselect and noop cycles (2) notes: 1. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 2. h = high; l = low; x = dont care; z = high impedance. cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments na 0 hl llxxxload read n+1 x x h x l x x x burst read n+2 a 1 hl llxlq 0 load read n+3 x x l h l x l q 0+1 deselect or stop n+4 x x h xlxlq 1 noop n+5 a 2 hl llxxzload read n+6 x x h x l x x z burst read n+7 x x l h l x l q 2 deselect or stop n+8 a 3 l l llllq 2+1 load write n+9 x x h x l l x z burst write n+10 a 4 l l lllxd 3 load write n+11 x x l h l x x d 3+1 deselect or stop n+12 x x h x l x x d 4 noop n+13 a 5 l l lllxzload write n+14 a 6 hl llxxzload read n+15 a 7 l l lllxd 5 load write n+16 x x h x l l l q 6 burst write n+17 a 8 hl llxxd 7 load read n+18 x x h x l x x d 7+1 burst read n+19 a 9 l l llllq 8 load write 53 04tbl 12 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x x l x x x clock setup valid n+2 x x x xxxlq 0 contents of address a 0 read out 53 04 tb l 13
6.42 12 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges burst write operation (1) burst read operation (1) write operation (1) notes: 1. h = high; l = low; x = dont care; z = high impedance.. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x h x l x x x clock setup valid, advance counter n+2 x x h xlxlq 0 address a 0 read out, inc. count n+3 x x h xlxlq 0+1 address a 0+1 read out, inc. count n+4 x x h xlxlq 0+2 address a 0+2 read out, inc. count n+5 a 1 hl llxlq 0+3 address a 0+3 read out, load a 1 n+6 x x h xlxlq 0 address a 0 read out, inc. count n+7 x x h xlxlq 1 address a 1 read out, inc. count n+8 a 2 hl llxlq 1+1 address a 1+1 read out, load a 2 5304 tbl 14 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x x x l x x x clock setup valid n+2 x x x x l x x d 0 write to address a 0 53 04 tbl 15 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup n+1 x x h x l l x x clock setup valid, inc. count n+2 x x h x l l x d 0 address a 0 write, inc. count n+3 x x h x l l x d 0+1 address a 0+1 write, inc. count n+4 x x h x l l x d 0+2 address a 0+2 write, inc. count n+5 a 1 l l lllxd 0+3 address a 0+3 write, load a 1 n+6 x x h x l l x d 0 address a 0 write, inc. count n+7 x x h x l l x d 1 address a 1 write, inc. count n+8 a 2 l l lllxd 1+1 address a 1+1 write, load a 2 53 04 tb l 16
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 13 read operation with clock enable used (1) write operation with clock enable used (1) notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. notes: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments na 0 h l l l x x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a 1 h l l l x x x clock valid n+3 x x x x h x l q 0 clock ignored, data q 0 is on the bus. n+4 x x x x h x l q 0 clock ignored, data q 0 is on the bus. n+5 a 2 hl llxlq 0 address a 0 read out (bus trans.) n+6 a 3 hl llxlq 1 address a 1 read out (bus trans.) n+7 a 4 hl llxlq 2 address a2 read out (bus trans.) 53 04 tb l 17 cycle address r/ w adv /ld ce (2) cen bw x oe i/o comments na 0 l l l l l x x address and control meet setup. n+1 x x x x h x x x clock n+1 ignored. n+2 a 1 l l lllxxclock valid. n+3 x x x x h x x x clock ignored. n+4 x x x x h x x x clock ignored. n+5 a 2 l l lllxd 0 write data d 0 n+6 a 3 l l lllxd 1 write data d 1 n+7 a 4 l l lllxd 2 write data d 2 53 04 tb l 18
6.42 14 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 3. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. read operation with chip enable used (1) write operation with chip enable used (1) notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o (3) comments n x x l h l x x ? deselected. n+1 x x l h l x x ? deselected. n+2 a 0 h l l l x x z address and control meet setup n+3 x x l h l x x z deselected or stop. n+4 a 1 hl llxlq 0 address a 0 read out. load a 1 . n+5 x x l h l x x z deselected or stop. n+6 x x l h l x l q 1 address a 1 read out. deselected. n+7 a 2 h l l l x x z address and control meet setup. n+8 x x l h l x x z deselected or stop. n+9 x x l h l x l q 2 address a 2 read out. deselected. 53 04 tbl 19 cycle address r /w adv/ ld ce (2) cen bw x oe i/o (3) comments n x x l h l x x ? deselected. n+1 x x l h l x x ? deselected. n+2 a 0 l l l l l x z address and control meet setup n+3 x x l h l x x z deselected or stop. n+4 a 1 l l lllxd 0 address d 0 write in. load a 1 . n+5 x x l h l x x z deselected or stop. n+6 x x l h l x x d 1 address d 1 write in. deselected. n+7 a 2 l l l l l x z address and control meet setup. n+8 x x l h l x x z deselected or stop. n+9 x x l h l x x d 2 address d 2 write in. deselected. 5304 tbl 20
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 15 1 2 3 4 20 30 50 100 200 d tcd (typical, ns) capacitance (pf) 80 5 6 5304 drw 05 , dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v +/-5%) figure 2. lumped capacitive load, typical derating ac test conditions (v ddq = 3.3v) dc electrical characteristics over the operating temperature and supply voltage range (1) (v dd = 3.3v +/-5%) figure 1. ac test load ac test load note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application and the zz pin will be internally pulled to vss if not actively driven. notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. 3. for i/os v hd = v ddq C 0.2v, v ld = 0.2v. for other inputs v hd = v dd C 0.2v, v ld = 0.2v. symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo input leakage current (1) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current v out = 0v to v ddq , device deselected ___ 5a vo l output low voltage i ol = +8ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -8ma, v dd = min. 2.4 ___ v 5304 tbl 21 symbol parameter test conditions 150mhz 133mhz 100mhz unit com'l ind com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2) 325 345 300 320 250 270 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2,3) 40 60 40 60 40 60 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2.3) 120 140 110 130 100 120 ma i sb3 idle power supply current device selected, outputs open, cen > v ih , v dd = max., v in > v hd or < v ld , f = f max (2,3) 40 60 40 60 40 60 ma i zz full sleep mode supply current device selected, outputs open cen v il , v dd = max., zz 3 v hd v in 3 v hd or v ld , f = fmax (2, 3) 40 60 40 60 40 60 ma 5304 tbl 22 input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 3v 2ns 1.5v 1.5v see figure 1 53 04 tbl 23 v ddq /2 50 w i/o z 0 =50 w 5304 drw 04 ,
6.42 16 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges ac electrical characteristics (v dd = 3.3v +/-5%, commercial and industrial temperature ranges) notes: 1. t f = 1/t cyc . 2. measured as high above 0.6v ddq and low below 0.4v ddq . 3. transition is measured 200mv from steady-state. 4. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 5. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 1ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz , which is a max. parameter (worse case at 70 deg. c, 3.135v). 6. commercial temperature range only. 150mhz (6) 133mhz 100mhz symbol parameter min. max. min. max. min. max. unit t cy c clock cycle time 6.7 ____ 7.5 ____ 10 ____ ns t f (1) clock frequency ____ 150 ____ 133 ____ 100 mhz t ch (2) clock high pulse width 2.0 ____ 2.2 ____ 3.2 ____ ns t cl (2) clock low pulse width 2.0 ____ 2.2 ____ 3.2 ____ ns output parameters t cd clock high to valid data ____ 3.8. ____ 4.2 ____ 5ns t cdc clock high to data change 1.5 ____ 1.5 ____ 1.5 ____ ns t cl z (3, 4,5) clock high to output active 1.5 ____ 1.5 ____ 1.5 ____ ns t chz (3, 4,5) clock high to data high-z 1.5 3 1.5 3 1.5 3.3 ns t oe output enable access time ____ 3.8 ____ 4.2 ____ 5ns t ol z (3,4) output enable low to data active 0 ____ 0 ____ 0 ____ ns t ohz (3,4) output enable high to data high-z ____ 3.8 ____ 4.2 ____ 5ns set up times t se clock enable setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sa address setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sd data in setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sw read/write (r/ w ) setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sadv advance/load (adv/ ld ) setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sc chip enable/select setup time 1.5 ____ 1.7 ____ 2.0 ____ ns t sb byte write enable ( bw x) setup time 1.5 ____ 1.7 ____ 2.0 ____ ns hold times t he clock enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns 5304 tbl 24
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 17 timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. a d v / ld ( c e n high, elim inates current l-h clock edge) o 2(a 2) t c d t h a d v p ipeline r ead (b urst w raps around to initial state) t c d c t c lz t c h z t c d t c d c r / w c lk c e n a d d r e s s o e d a t a o u t t h e t s e a 1 a 2 o 1(a 2) o 1(a 2) t c h t c l t c y c t s a d v t h w t s w t h a t s a t h c t s c b urst p ipeline r ead p ipeline r ead b w 1 - b w 4 5304 drw 06 c e 1 , c e 2 (2) q (a 2+ 3 ) q (a 2 ) q (a 2+ 2 ) q (a 2+ 2 ) q (a 2+ 1 ) q (a 2 ) q (a 1 ) ,
6.42 18 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of write cycles (1,2,3,4,5) t h e t s e r / w a 1 a 2 c lk c e n a d v / l d a d d r e s s o e d a t a in t h d t s d t c h t c l t c y c t h a d v t s a d v t h w t s w t h a t s a t h c t s c b urst p ipeline w rite p ipeline w rite p ipeline w rite t h b t s b (b urst w raps around to initial state) t h d t s d ( c e n high, elim inates current l-h clock edge) (2) d ( a 2+ 2 ) d ( a 2+ 3 ) d (a 1 ) d (a 2 ) d (a 2 ) 5304 drw 07 b w 1 - b w 4 c e 1, c e 2 d (a 2+ 1 ) .
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 19 t h e t s e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s c e 1 , c e 2 (2) b w 1 - b w 4 d a t a o u t q (a 3 ) q (a 1 ) q (a 6 ) q (a 7 ) t c d r ead t c h z 5304 drw 08 w rite t c lz d (a 2 ) d (a 4 ) t c d c d (a 5 ) w rite t c h t c l t c y c t h w t s w t h a t s a a 4 a 3 t h c t s c t s d t h d t h a d v t s a d v a 6 a 7 a 8 a 5 a 9 d a t a in t h b t s b o e r ead r ead , , notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of combined read and write cycles (1,2,3)
6.42 20 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. timing waveform of cen operation (1,2,3,4) t h e t s e r / w a 1 a 2 c lk c e n a d v / l d a d d r e s s b w 1 - b w 4 o e d a t a o u t q (a 3 ) t c d t c lz t c h z t c h t c l t c y c t h c t s c d (a 2 ) t s d t h d t c d c a 4 a 5 t h a d v ts a d v t h w t s w t h a t s a a 3 t h b t s b d a t a in q (a 1 ) 5304 drw 09 q (a 1 ) b (a 2 ) c e 1 , c e 2 (2)
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 21 timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. r / w a 1 c lk a d v / l d a d d r e s s o e d a t a o u t q (a 1 ) t c d t c lz t c h z t c d c t c h t c l t c y c t h c t s c t s d t h d a 5 a 3 t s b d a t a in t h e t s e a 2 t h a t s a a 4 t h w t s w t h b c e n t h a d v t s a d v 5304 drw 10 q (a 2 ) q (a 4 ) d (a 3 ) b w 1 - b w 4 c e 1, c e 2 (2) ,
6.42 22 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 100-pin plastic thin quad flatpack (tqfp) package diagram outline
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 23 119 ball grid array(bga) package diagram outline
6.42 24 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges 165 fine pitch ball grid array (fbga) package diagram outline
6.42 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperatur e ranges 25 timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out t ohz t olz t oe valid 5304 drw 11 , 100 pin plastic thin quad flatpack, (tqfp) 119ballgridarray(bga) 165 fine pitch ball grid array (fbga) s power xx speed xx package pf bg bq idt xxxx 150 133 100 clock frequency in megahertz 5304 drw 12 device type idt71v65603 idt71v65803 256kx36 pipelined zbt sram 512kx18 pipelined zbt sram x process/ temperature range blank i commerical (0 to 70c) industrial (-40 to 85c) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc.
6.42 26 idt71v65603, idt71v65803, 256k x 36, 512k x 18, 3.3v synchronous srams with zbt ? ? ? ? ? feature, 3.3v i/o, burst counter, and pipelined outputs commercial and industrial temperature ranges datasheet document history 12/31/99 created new datasheet from obsolete devices idt71v656 and idt71v658 03/04/00 pg. 1,14,15 removed 166mhz speed grade offering; added 150mhz speed grade offering 04/20/00 pg. 5,6 added jtag test pins to tqfp pin configuration; removed footnote pg. 5,6 add clarification note to recommended operating temperature and absolute max ratings tables pg. 7 add note to bga pin configuration; correct typo within pinout pg. 21 insert tqfp package diagram outline 05/23/00 add new package offering, 13 x 15mm 165 fbga pg. 23 correction in bg 119 package diagram outline 07/28/00 add industrial temperature pg. 2 correction v ddq 3.3v i/o supply pg. 5-8 remove jtag offerings, refer to idt71v656xx and idt71v658xx device errata sheet pg. 7 correct pin b2 pg. 8 change pin b1 to nc pg. 23 update bg119 package diagram outline 11/04/00 pg. 8 add note to pin n5 on bq165 pinout, reserved for jtag trst pg. 15 add izz parameter to dc electrical characteristics 10/16/01 pg. 16 changed sub-header to include commercial and industrial temperature ranges. corrected the tch from 22ns to 2.2ns and tsadv from 20ns to 2.0ns. 12/04/02 pg. 1-25 changed datasheet from prelininary to final release. pg. 15 added i temp to 150mhz. pg. 16 corrected typo from 22 to 2.2. 12/19/02 pg. 1,2,5,6, removed jtag functionality for current die revision. 7,8 pg. 7 corrected pin configuration on the x36, 119bga. switched pins i/o0 and i/op1.

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